1. Field
The present disclosure relates generally to processing systems, and more specifically, to a bus access arbitration scheme in a processing system.
2. Background
Computers have revolutionized the electronics industry by enabling sophisticated processing tasks to be performed with just a few strokes of a keypad. These sophisticated tasks involve an incredibly high number of complex components that communicate with one another in a fast and efficient manner using a bus. A bus is a channel or path between components in a computer or other computational device.
Many buses have been traditionally implemented as shared buses. A shared bus provides a means for any number of components to communicate over a common path or channel. In recent years, shared bus technology has been replaced to a large extent by point-to-point switching connections. Point-to-point switching connections provide a direct connection between two components on the bus while they are communicating with each other. Multiple direct links may be used to allow several components to communicate at the same time. A bus arbiter may be used to manage communications over the bus.
A computer implementing a bus architecture may include any number of processing components connected to one or more shared resources, such as memory. One or more processors (bus master) may initiate a bus transaction by requesting access from the bus arbiter. The bus arbiter determines the sequence in which the processors will be granted access to the bus based on a pre-determined algorithm. Various bus access arbitration schemes have been implemented in the past to manage these transactions. A fairly common approach is a round robin arbitration scheme which allocates bandwidth evenly across all processing components, but has no notion of latency requirements. Another common approach is a fixed priority arbitration scheme which has some notion of latency requirements, but severely degrades low priority processors which may require high bandwidth. Time-division-multiplexing is probably a better solution than a round robin or fixed priority based arbitration scheme, but it is difficult to predict when a particular processor may require access to the bus. Accordingly, there is a need in the art for a bus access arbitration scheme that provides the ability to allocate bandwidth allocation while still maintaining latency requirements for the processors on the bus.